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[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26624 | Author: QQ | Hits:

[VHDL-FPGA-Verilog] 8LEDverilog

Description: //led.v /*------------------------------------- LED显示模块：led(CLK,AF,ADDR,DATA) 功能： 显示 注意事项： 8位LED 参数： CLK:扫妙时钟输入，推荐1kHz AF:数码管输出，a～h ADDR:数码管选择位数出，0~2 DATA:显示数据输入0~9999 9999 编写人： 黄道斌 编写日期： 2006/07/13 -------------------------------------*/-//led.v /*------------------------------------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : digital control options from the median, 0 ~ 2 DATA : data show that the importation of 0 ~ 9999 9999 prepared : Huang Daobin preparation date : 2006/07/13-------------------------------------*/
Platform: | Size: 1024 | Author: 黄道斌 | Hits:

[Special Effects] MedianFilter33

Description: 3*3 中值滤波的verilog代码实现，已经调试通过！欢迎提出宝贵意见！-3* 3 filtering to achieve the verilog code has been adopted debugging! Welcomed the valuable advice!
Platform: | Size: 49152 | Author: | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] median

Description: 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
Platform: | Size: 1775616 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] median_filterCode

Description: 采用快速中指滤波算法实现图像的中值滤波，使用VHDL语言ISE环境-Image Median Filter
Platform: | Size: 12288 | Author: 若谙 | Hits:

[Other] Appendix11

Description: Median Filter In Verilog
Platform: | Size: 222208 | Author: zerocool | Hits:

[Special Effects] Code_for_MedianFilter33

Description: 3x3中值滤波器的FPGA实现(VERILOG)-3x3 median filter FPGA implementation (VERILOG)
Platform: | Size: 53248 | Author: tom | Hits:

[VHDL-FPGA-Verilog] MovingAverageFilter

Description: This zip file contains the moving average filter code written in verilog HDL
Platform: | Size: 1147904 | Author: Jagan | Hits:

[Software Engineering] median

Description: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Platform: | Size: 2048 | Author: 刘文英 | Hits:

[Books] FPGAmidxilinx

Description: 基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序-FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog
Platform: | Size: 276480 | Author: xutongxue | Hits:

[VHDL-FPGA-Verilog] MEDIAN.v

Description: fpga 的 median的verilog实现-median of verilog implementation
Platform: | Size: 1024 | Author: xyz | Hits:

[VHDL-FPGA-Verilog] 3-3-median-filter

Description: verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
Platform: | Size: 51200 | Author: | Hits:

[VHDL-FPGA-Verilog] medianfilter

Description: 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
Platform: | Size: 3262464 | Author: 钱军 | Hits:

[Other] median

Description: A median filter in verilog
Platform: | Size: 2048 | Author: Ali | Hits:

[VHDL-FPGA-Verilog] 图像中值滤波FPGA实现V1.0

Description: 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
Platform: | Size: 30031872 | Author: gxgone | Hits:

[Other] median_filter

Description: 这个verilog程序实现了图像中值滤波，处理实时性很强，有兴趣的可以参考(This Verilog program implements the median filter in the image, the processing is very real, and the interest can be referred to)
Platform: | Size: 1950720 | Author: zengang | Hits:

[VHDL-FPGA-Verilog] VIP_RAW2RGB2Gray_Medium_Sobel_Erosion_Dilation

Description: 通过纯HDL逻辑实现,对ov7725摄像头进行图像采集,存储,处理,包括中值滤波,边缘检测等经典图像算法实现(Through the realization of pure HDL logic, image acquisition, storage and processing of ov7725 camera, including median filtering, edge detection and other classic image algorithms.)
Platform: | Size: 931840 | Author: SakuraForever | Hits:

[VHDL-FPGA-Verilog] module_average_filter

Description: 一个中值滤波算法的verilog实现。。。。。。。(Verilog implementation of a median filtering algorithm)
Platform: | Size: 4096 | Author: 兴鹏 | Hits:
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